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167# oldboy
[quote]I think you guys are in the right ballpark. All else being equal, with this design, more Idss is better. Running at 50% of Idss or even to 80% is best, the jfet can still put out to more than 100% on dynamic peaks without anything obvious going on. However operating at 0 bias, or 100% is iffy.
The higher Idss part gives you a lower value load resistor that extends the open loop bandwidth. The higher percentage of Idss you bias, does the same thing.
However, a medium Idss part will work OK, if you don't starve it.
__________________
"Condemnation without Examination is Prejudice"
[21st June 2010, 07:40 PM / John Curl quote]
中译文:
我认为你们在正确的领域内思考.对于这个设计,在同等条件下比较,越大的Idss越好.运行在50%(30ma)或80%(30ma)是很好的,这JFET仍然能够产生超过100%的动态峰值没有明显影响.然而运作在零偏,或100%是有问题的.
越高的Idss给予你更低阻值的负载电阻这扩宽了开环频率.你偏置的值占Idss的百分比越大也同样的效果.然而,一个中等Idss的元件将工作良好,如果你不是抱着很高的期望的话.
没有分析研究的指责是偏见. |
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