The PCM1702 accepts TTL compatible logic input levels.
PCM1702接受TTL兼容的逻辑输入电平。
The data format of the PCM1702 is binary two’s complement (BTC) with the most significant bit (MSB) being first in the serial input bit stream.
PCM1702的数据格式是二进制补码(BTC)，最大有效位(MSB)先。
Table II describes the exact relationship of input data to voltage output coding.
表二描述输入数据与电压输出编码的确切关系。
Any number of bits can precede the 20 bits to be loaded, since only the last 20 will be transferred to the parallel DAC register after Latch Enable (Pin6 <CM1702P>, Pin7 <CM1702U>, LE) has gone low.
有些位数可以先于20位被加载，因为LE低电平时只将末20位转移到并行DAC寄存器。
All DAC serial input data (Pin1, DATA) bit transfers are triggered on positive clock (Pin2, CLOCK), edges.
串行输入数据传输由时钟正向脉冲的边沿触发。
The serial-to-parallel data transfer to the DAC occurs on the falling edge of Latch Enable.
传输到DAC的串转并数据在LE下降沿生效。
The change in the output of the DAC occurs at a rising edge of the 4th clock of the CLOCK after the falling edge of Latch Enable.
DAC的输出的变化发生在LE下降沿开始后的第4个时钟周期的上升沿。
Refer to Figure 2 for graphical relationships of these signals.
参阅图2对这些信号的图形关系。
NOTES :
(1) If clock is stopped between input of 20-bit data words, "Latch" Enable (LE) must remain low until after the first clock cycle of the next 20-bit data word stream.
如时钟在20位数据串输入时停了（会么？没电池了？）， LE仍须保持低电平直至下一串20位数据流开始的第一个时钟周期后。
(2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge.
数据格式是二进制补码(BTC)。各个数据位分别在相应的时钟上升沿移入。
(3) Latch Enable (LE) must remain low at least one clock cycle after going negative.
LE拉低后必须保持低电平至少一个时钟周期。
(4) Latch Enable (LE) must be high for at least one clock cycle before going negative.
LE拉低前必须保持至少一个时钟周期的高电平。
(5) I OUT changes on positive going edge of the 4th clock after negative going edge of Latch Enable (LE).
I OUT的变化发生在LE下降沿后的第4个时钟脉冲上升沿。
楼主
发表于 2014-3-26 21:38
），对调异或输出后，声道正确了，声音还那样。
