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发表于 2013-9-16 17:29 | 显示全部楼层
本帖最后由 BG5CJT 于 2013-9-16 17:54 编辑

原文转载于:
http://hifiduino.wordpress.com/2013/08/11/the-hifidiy-es9018-dac/
作者不断更新中

hifiduino1.jpg

temp.jpg


以下原文转载:

Just received the Hifidiy ES9018 DAC.

01.jpg
HifiDIY has become the China distributor of ESS DAC products and has embarked in producing, in ollaboration with ESS Technologies, a DIY-friendly version of the ES9018 DAC.

I was able to obtain a version of the board delivered with the optional components installed by the people of HifiDIY. The standard offering of the DAC board only includes the surface mount components as shown in the second photo below:
02.jpg

03.jpg
A DIYer is expected to select and install the remaining components (the output stage components, including the op-amps, the AVCC op-amp based supply and the decoupling capacitors of the on-board regulators). As can be seen, the designers opted to use through-hole components for wider diy appeal.

IMPLEMENTATION

This is a “basic” implementation following the guidelines of the ESS datasheet but at the same time a vast improvement over the ESS evaluation board with respect to PCB material and choice of components.

04.jpg
Here is the DAC chip and the power lines decoupled with C0G ceramic capacitors. The chip has a date code of 033 (likely week 03 of 2013). Pretty new batch.
Some have negatively commented over the large distance of the decoupling capacitors from the pins.
05.jpg
But as can be seen the photos the distance is not really “so large”. I believe a “diy-friendly” approach was more important to HIFIdiy than the potential “ultimate performance/measurement”.
As can also be seen, there is sufficient clearance between the components for a diyer to solder or rework the DAC chip even with the decoupling capacitors in place.
The straight board trace from the bottom left is the spdif input line to the DAC chip4-LAYER PCB
06.jpg

07.jpg

This is a very high quality 4-layer PCB with superb finish. Just for show, the 4-layers can be seen in this “window”. Front side of the board:
08.jpg

Back side of the board:
09.jpg

AVCC SUPPLY

The 3.3v AVCC supply which is the most important supply for the DAC, uses a AD797 opamp (0.9 nV/√Hz noise) [datasheet:link]. It is implemented as a voltage follower per datasheet. The 3.3V reference signal is provided by the local 3.3V regulator.

Parts:

AD797: [Digikey:link]

Electrolytic caps: 10uF, 50V. These are bipolar “TOWA” brand which are not available in the US market. Can substitute with any “good” electrolytic cap such as Panasonic FM or FR or ELNA SILMIC [Mouser:link]

The decoupling capacitors are Vishay ERO MKP 1837 [link] 0.1uF, 160V. These ERO brand are not available in the US market. Vishay-branded MKP 1837 are available [Mouser:link]. These are pricey caps at $1.32 each. Can substitute with WIMA MKP2/4 for lower price.

10.jpg

The 3.3V reference voltage is further filtered with a CRC filter. Note also the compensation resistor for the opamp to prevent oscillation. This is indicated in the datasheet: “With the AD797, additional input series damping is required for stability with direct output to input feedback. A 100 Ω resistor (R1) in the inverting input (Figure 37) is sufficient; the 100 Ω balancing resistor (R2) is recommended but is not required for stability.”

11.jpg

CLOCK

Clock and clock supply is implemented with an ADP150 regulator[link] (Ultra low noise: 9 μV rms, independent of VOUT). The “LEJ” marking signifies a 3.3 Vout part. These parts are already installed in the basic configuration.

The input to the regulator is taken from the 5V external supply that also feeds the on-board 3.3V and 1.2V regulator. C5 and C5A are output capacitors for the regulator. Notice that there is no input capacitor except for the output capacitor of the 5V supply. Some improvement could be had by locating an input capacitor near the regulator and by ensuring the 5V external supply is well implemented.

The resistor (R5A) is to pull-up the enable line of the clock.

12.jpg

The Crystek CCHD-100 MHz oscillator[link] has become the standard for ES9018-based DAC implementations.  This part is a “-50″ part meaning 50 ppm frequency stability. Other implementations have used a “-25″ as in 25 ppm frequency stability.  Whether 25 ppm or 50 ppm, they all have the same jitter specification. Whether you can purchase a “-25″ or “-50″ parts likely depends on availability. A quick check on Digikey, shows that the “-25″ part is out of stock…

13.jpg

SINGLE INPUT

This board only supports a single input (and because it only uses DATA 1 (a single data line), it only supports spdif input).

One can select between the transformer-isolated (+/FG) or the non-isolated input (+/G), but can only use one input. The SPDIF input level is boosted by a TI LMV7219 comparator[link] to the 3.3V required by the DAC.

14.jpg

15.jpg

16.jpg

I2S HACK?

It is possible to support I2S inputs if one is capable of tapping to the chip pins. According to these photos, the remaining input pins are not connected to anything.

17.jpg

18.jpg

19.jpg

with steady hands and a proper soldering tip, it is quite possible to connect the I2S/DSD inputs to external wiring. (For now I think I would just leave it as is since i have other ES9018 DACs with proper output connections)

Shown below is a 30 gauge wire in comparison with the pins of the ES9018 chip
20.jpg

The board is designed to work without a microprocessor. In “hardware mode”, upon power-in, the chip defaults to stereo and “auto input” with SPDif input assigned to DATA1.  Even though in this mode one can also use I2S input, I think ease of use/configuration was a desired design criteria for this board and therefore the other inputs were not been enabled. (Switching between SPDiF and I2S would require mechanical switching as DATA1 is shared between SPDIF and I2S).

However, the I2C inputs are available for software control such as for using the digital volume control and the selection of the built in filters.

21.jpg

ON BOARD POWER SECTION

In addition to AVCC and the clock supply, there are 4 additional on board supplies. From left to right:

Digital 3.3V for powering the DAC’s 3.3V supply, the spdif comparator and also as a reference to 3.3V AVCC; digital 1.2V for powering the DAC’s 1.2V supply; +12V and -12V for powering the output stage opamps, and the AVCC opamp. So in total, there are 6 local regulators.

The popular low noise LT1963A[link] and the equivalent LT3015[link]is a good choice .

22.jpg

Apparently it uses Panasonic FC capacitors (the gray ones). These are not available in the US.

Apparently the supply of parts is much greater in that part of the world (where a lot of stuff is manufactured) -whether new or old stock or even special runs that the factories made. HIFIdiy made great efforts to obtain authentic parts, so I am confident that there are no questionable parts.

The aluminum electrolytic decoupling caps can be replaced with newer Panasonic FM or FR with the same or greater values. For example: Panasonic FR 220uV, 50v [Mouser:link]

With regard to the WIMA film decoupling caps, here is a link explaining the different series: [diyaudio: link]

The green ones appear to be WIMA FKP2 (Film and Foil caps)[link].

23.jpg

The input capacitor decoupling is the same for each regulator: an aluminum high value electrolytic capacitor with a low value film capacitor in parallel. The output capacitor decoupling varies, but they are equally effective. The two output film capacitors (red WIMAs) may not be required as each opamp already has local decoupling.

24.jpg

The 1.2 supply is a “lowly” LD1117 fixed 1.2V regulator [link]. It is implemented a per datasheet. The resistor (a 120 ohm shunt at the output) is a requirement for the 1.2V fixed regulator. I would have liked to see a lower noise regulator such as the LT1963.

25.jpg

It would be beneficial to increase the value of the output capacitor for this 1.2v regulator.

There are 8 LEDs indicating power supply operation and signal lock status.

26.jpg

OUTPUT STAGE

The output stage is implemented as per the ES9018 datasheet. The only difference is that for the balanced output, it is buffered.

27.jpg

28.jpg

Use of top-notch components.
29.jpg

30.jpg

The opamps are the AD797 “B” grade (which is the higher grade of the AD797 opamp) and only available in SOIC packages. Thus the use of chip carriers.
31.jpg

HIFIdiy developed teflon PCB adapters for the SOIC opamps. According to them, this preserves the performance of the opamps.
32.jpg

Vishay 102K Foil resistors [link]. The decoupling capacitors are Vishay ERO MKP 1837 [link]. (ERO was an original ROEDERSTEIN brand). This brand of capacitors is not widely available anymore.
33.jpg

34.jpg

Either these are old stock or only available in the Asia market.

The balanced output is buffered with a AD826 opamp [link]. “The AD826 is a dual, high speed voltage feedback op amp. It is ideal for use in applications which require unity gain stability and high output drive capability, such as buffering and cable driving. The AD826 features high output current drive capability of 50 mA min per amp, and is able to drive unlimited capacitive loads.”

35.jpg

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发表于 2013-9-16 17:50 | 显示全部楼层
英文太差 看不懂 哈哈

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发表于 2013-9-16 17:54 | 显示全部楼层
好东西。。。。。。就等了

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发表于 2013-9-16 18:20 | 显示全部楼层
求大神翻译

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发表于 2013-9-16 18:22 | 显示全部楼层
本帖最后由 maxma123 于 2013-9-16 18:28 编辑

这个是制作示范帖。英文没看懂。

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发表于 2013-9-16 19:30 | 显示全部楼层
图片很养眼,鸟文看不懂。
头像被屏蔽

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DAC7天下无敌

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发表于 2013-9-16 19:46 | 显示全部楼层
提示: 作者被禁止或删除 内容自动屏蔽

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发表于 2013-9-16 21:16 | 显示全部楼层
厚此薄彼啊,在这里发是只放图不说话,在英文网站就有图文。

1.JPG

2.JPG

请看这两个图的焊点和防爆纹,说不是同一块板谁都不信。

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发表于 2013-9-17 00:14 | 显示全部楼层
8楼才是亮点呀.........

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发表于 2013-9-17 00:49 | 显示全部楼层
佩服,看到元件马上能报出具体型号的都是牛人……

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发表于 2013-9-17 08:40 | 显示全部楼层
本帖最后由 别时方觉依依 于 2013-9-17 08:42 编辑

8楼才是亮点
是版主去国外做推广么?

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发表于 2013-9-17 09:16 来自手机端 | 显示全部楼层
乌龙了吧

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社区贡献 新人进步

发表于 2013-9-17 09:34 | 显示全部楼层
是摄影技术示范吗?

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发表于 2013-9-17 09:54 | 显示全部楼层
交钱了两个月了,看到得资料没有国外的全。真TM的坑!

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发表于 2013-9-17 10:03 | 显示全部楼层
图片很清晰,不错

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发表于 2013-9-17 12:23 | 显示全部楼层
这帖子真是无语

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发表于 2013-9-17 12:26 来自手机端 | 显示全部楼层
看到这儿我也有点无语,还是国外的月亮圆。

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发表于 2013-9-17 12:32 | 显示全部楼层
本帖最后由 stars 于 2013-9-17 12:44 编辑

在国外的网站上看这个板子更漂亮

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发表于 2013-9-17 12:58 | 显示全部楼层
当年英语逃课太多。。今天首次后悔

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发表于 2013-9-17 13:23 | 显示全部楼层
MARK
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