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楼主 |
发表于 2011-6-12 23:03
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用CDCE913也是看见TI推荐这样做,才敢动手,不可以想当然。
用CDCE913内部的VCXO控制远比一般压控晶振方便,而且性价比超高。
有兴趣的朋友可以去TI网找scaa088文件。
英文介绍如下:
For many audio applications a sampling clock or word clock of 44.1 kHz or 48.0 kHz is available through a
distribution network. The audio data converters in such applications are often Delta-Sigma,
modulator-based devices that can over-sample the signal by a factor of up to 512, resulting in a system
clock of 22.5792 MHz or 24.5760 MHz. This system clock must be synchronized with the low-frequency
sampling clock using a phase-locked loop (PLL), but the sampling clock is often too low in frequency for
use with many PLL-based clock drivers. Some audio PLLs can accept the low frequency sampling clock,
but create so much jitter on the system clock, that performance degrades.
The CDCE913 is a PLL-based clock driver with a VCXO input. It can drive a fundamental mode crystal in
the range of 8 to 32 MHz or receive a 1.8 V LVCMOS clock ranging from 8 to 160 MHz. Like most PLLs, if
the PLL internal to the CDCE913 is used to generate the system clock, it generates too much long-term
jitter; even though it has an excellent short-term period jitter performance of typically 60 ps peak-to-peak.
If we use its VCXO capabilities for synchronization and create a very low-loop bandwidth PLL, using an
external phase comparator (CD74HC4046A) and loop filter; a complete PLL is formed with excellent
long-term jitter performance and jitter-cleaning properties. |
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