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发表于 2023-2-18 08:45
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In an R-2R DAC design with supply voltages exceeding ±5V, large voltage glitches (up to 1.5V) can occur during the DAC's major-carry transitions. These glitches can propagate through the output buffer amplifier and appear at output. The slewing of the level shifters that control the top (VREF+) and bottom (VREF-) single-pole double-throw switches (S0 to SN) causes the glitches (Figure 1). If each switch of the "inverted" R-2R ladder were turned on and/or off instantaneously, glitch amplitudes at the DAC output (or input of the output buffer amplifier) would be small. However, switches do not switch instantaneously; in fact, to avoid crowbar current between outputs of the two reference buffers, the switches employ a break-before-make connection. The associated time delay can produce very large glitches during DAC code transitions that degrade the dynamic performance specification "glitch impulse energy."
在电源电压超过±5V的R-2R DAC设计中，在DAC的主要进位转换期间可能会出现较大的电压毛刺（高达1.5V）。这些毛刺可以通过输出缓冲放大器传播并出现在输出端。控制顶部（VREF+）和底部（VREF-）单极双掷开关（S0至SN）的电平移位器的回转导致了故障（图1）。如果“反相”R-2R梯形图的每个开关瞬时打开和/或关闭，DAC输出（或输出缓冲放大器的输入）处的毛刺振幅将很小。然而，开关不会瞬时切换；事实上，为了避免两个参考缓冲器的输出之间的撬棍电流，开关在连接之前采用断开。相关的时间延迟会在DAC代码转换期间产生非常大的毛刺，从而降低动态性能规范“毛刺脉冲能量”
Figure 1. Simplified DAC circuit.
One way to reduce glitch energy is to connect a large capacitor between the DAC output and ground. The lowpass-filter combination of RDAC and C reduces the amplitude of the glitch. However, to reduce the glitch significantly, the capacitance value must be large. Thus, this approach increases the DAC's settling time considerably.
减少毛刺能量的一种方法是在DAC输出和接地之间连接一个大电容器。RDAC和C的低通滤波器组合降低了毛刺的幅度。然而，为了显著减少毛刺，电容值必须较大。因此，这种方法大大增加了DAC的稳定时间。
Another deglitching technique is to use an external track/hold (T/H) amplifier following the DAC output. One advantage of this approach is that glitches at the DAC output can be eliminated completely (in principle). However, external one shot and deglitch timing control logic (in addition to the T/H amplifier) are required. Thus, the interface between the DAC, the deglitch timing control circuit, and the T/H amplifier can be fairly cumbersome.
另一种消除失真技术是在DAC输出之后使用外部跟踪/保持（T/H）放大器。这种方法的一个优点是可以完全消除DAC输出处的毛刺（原则上）。然而，需要外部单触发和消隐定时控制逻辑（除T/H放大器外）。因此，DAC、消隐时序控制电路和T/H放大器之间的接口可能相当麻烦。
Integrating the T/H amplifier on the same chip as the DAC eliminates the cumbersome interface (Figure 2). The deglitch T/H amplifier is placed immediately following the buffered DAC output. Using this technique, a smart deglitch circuit has been developed that significantly reduces the digital-to-analog glitch impulse energy without increasing settling time.
将T/H放大器集成在与DAC相同的芯片上，消除了繁琐的接口（图2）。消隐T/H放大器位于缓冲DAC输出之后。使用该技术，开发了一种智能消隐电路，该电路在不增加稳定时间的情况下，显著降低了数模假脉冲能量。
Figure 2. Integrated T/H deglitch architecture.
Smart DAC Deglitch Circuit
智能DAC Deglitch电路
Because the glitch occurs right after a DAC is updated and disappears within the first few microseconds, if the DAC output and output buffer amplifier input are decoupled when the DAC is updated and stay decoupled until the glitch disappears, the glitch will not pass through the output buffer amplifier. As shown in Figure 2, this solution uses a T/H concept to eliminate glitches. Before the DAC is updated, switch SW1 is closed. The sampling capacitor samples the DC level of the previous DAC code. During a digital code transition, as the DAC is being updated the switch is opened and the capacitor (CH) holds the DC level of the previous DAC code. The amplifier output is maintained at this DC level while the glitch occurs. After the glitch disappears, the switch closes again. Unlike the lowpass-filter technique discussed in the previous section, the value of the T/H capacitor can be much smaller, because this capacitor is used to hold the DC level of the previous DAC code, as opposed to reducing the amplitude of a glitch. Small glitches can still occur when the T/H switch is turned on or off due to charge sharing and injection, but the associated glitch amplitude is much smaller.
由于故障发生在DAC更新之后，并在最初几微秒内消失，如果DAC更新时DAC输出和输出缓冲放大器输入解耦，并保持解耦，直到故障消失，则故障将不会通过输出缓冲放大器。如图2所示，该解决方案使用T/H概念来消除故障。在DAC更新之前，开关SW1闭合。采样电容器对先前DAC代码的DC电平进行采样。在数字代码转换期间，当DAC正在更新时，开关断开，电容器（CH）保持先前DAC代码的DC电平。当故障发生时，放大器输出保持在该DC电平。故障消失后，开关再次闭合。与前一节中讨论的低通滤波器技术不同，T/H电容器的值可以小得多，因为该电容器用于保持先前DAC代码的DC电平，而不是减小毛刺的幅度。当T/H开关由于电荷共享和注入而打开或关闭时，仍可能发生小故障，但相关的故障幅度要小得多。
Implementation Techniques
实施技术
Although combining the DAC output amplifier with a T/H appears obvious intuitively, this presents some design challenges during the actual implementation. For example, in some applications, a large DAC output swing is required. Therefore, the sampling switch (SW1) must operate with high-voltage potentials. This requirement limits the T/H implementation to a handful of processes having the required high breakdown voltage MOS switches. Another challenge is that the base current of the output amplifier's bipolar input pair can cause an offset voltage (IBASE × RSW) across the switch (SW1). Finally, charge injection and clock feedthrough are additional T/H circuit specifications that need to be considered.
尽管将DAC输出放大器与T/H组合在一起直观上看起来很明显，但这在实际实施过程中带来了一些设计挑战。例如，在某些应用中，需要较大的DAC输出摆幅。因此，采样开关（SW1）必须在高电压下工作。这一要求将T/H实现限制为具有所需高击穿电压MOS开关的少数工艺。另一个挑战是输出放大器的双极输入对的基极电流会在开关（SW1）两端产生偏移电压（IBASE×RSW）。最后，电荷注入和时钟馈通是需要考虑的附加T/H电路规范。
An Improved Deglitch Circuit
一种改进的Deglitch电路
With a unity-gain buffer amplifier following the DAC output, the sampling switch must have a high breakdown voltage. However, if the amplifier's gain is greater than one (n > 1), the required switch breakdown voltage will be reduced by a factor of n. This helps to relax the process requirements as they relate to the DAC and the switch. Figure 3 shows the architecture of this circuit.
对于DAC输出之后的单位增益缓冲放大器，采样开关必须具有高击穿电压。然而，如果放大器的增益大于1（n>1），所需的开关击穿电压将降低n倍。这有助于放松与DAC和开关相关的工艺要求。图3显示了该电路的架构。
Figure 3. An improved deglitch circuit.
图3。一种改进的消隐电路。
Designating VSW as the switch voltage that controls the sampling switch, the process breakdown voltage (VBREAKDOWN) limits the maximum value of VSW. By setting n>Vout (MIN/MAX)/VBREAKDOWN, the high-voltage concerns are mitigated.
将VSW指定为控制采样开关的开关电压，过程击穿电压（VBREAKDOWN）限制VSW的最大值。通过设置n>Vout（MIN/MAX）/VBRAKDOWN，高压问题得以缓解。
Eliminating Offset Due to Non-zero Base Current
消除非零基极电流引起的偏移
To eliminate the base current of the sampling switch, differential charge cancellation can be used, as shown in Figure 4.
为了消除采样开关的基极电流，可以使用差分电荷消除，如图4所示。
Figure 4. Differential charge cancellation.
图4。差分充电取消。
SW2 is equal to SW1, and both see the same impedance. The equivalent resistance is equal to R, and the equivalent capacitance is equal to CH.
SW2等于SW1，两者的阻抗相同。等效电阻等于R，等效电容等于CH。
This architecture improves the circuit performance; however, there are still a few concerns that need to be addressed. First, when SW1 and SW2 are both opened, there is no feedback path for the output amplifier; the amplifier is operating open loop. Second, the hold capacitor at the inverting input of the amplifier can cause additional phase shift, reducing the op amp's phase margin (PM).
这种结构提高了电路性能；然而，仍有一些问题需要解决。首先，当SW1和SW2都打开时，输出放大器没有反馈路径；放大器开环工作。其次，放大器反相输入端的保持电容会导致额外的相移，从而降低运算放大器的相位裕度（PM）。
Pole-Zero Architecture for the Deglitch Circuit
Deglitch电路的零极点结构
With a slight change in the amplifier feedback network, the circuit can address the phase-shift problem. As shown in Figure 5, the equivalent impedance at both sides of switches SW1 and SW2 are matched. This circuit effectively adds a zero at the pole location in the amplifier feedback network that compensates for the added phase shift and reduced phase margin of Figure 4.
通过对放大器反馈网络的轻微改变，该电路可以解决相移问题。如图5所示，开关SW1和SW2两侧的等效阻抗匹配。该电路有效地在放大器反馈网络中的极点位置处添加零点，以补偿图4中增加的相移和减少的相位裕度。
Figure 5. Complete architecture.
图5。完整的架构。
With this configuration, there is no phase shift from VOUT to VINN-. When SW2 opens, C1 and C2 maintain the negative feedback. For the pole-zero cancellation, the equivalent feedback network is shown in Figure 6.
使用此配置，从VOUT到VINN-没有相移。当SW2打开时，C1和C2保持负反馈。对于零极点消除，等效反馈网络如图6所示。
Figure 6. Equivalent circuit of feedback network.
图6。反馈网络的等效电路。
Mathematically, the advantage of this circuit, namely the pole-zero cancellation, is derived as follows:
从数学上讲，该电路的优点，即零极点消除，如下所示：
Test Results
测试结果
This smart deglitch circuit for the voltage DAC technique is currently used in the MAX5839, a 13-bit, octal, high-voltage DAC. Test measurements reveal that the digital-to-analog glitch energy is up to 10 times' smaller than that of other devices on the market. The following plot shows the test results.
这种用于电压DAC技术的智能消隐电路目前用于MAX5839，一种13位八进制高压DAC。测试测量显示，数字到模拟的故障能量比市场上其他设备的小10倍。下图显示了测试结果。
Figure 7. Glitch amplitude during a major-carry transition.
图7。主要进位转换期间的闪烁幅度。
Conclusions
结论
Using a T/H amplifier technique for deglitch circuits, we achieve very small glitches (typically 10mV to 20mV) at the DAC output during major-carry transitions. By implementing pole-zero cancellation in the RC feedback network, the additional phase shift due to the hold capacitor is eliminated and the stability of the output amplifier is maintained. When the sampling switch is opened, negative feedback is still employed via capacitors C1 and C2. Additionally, base-current cancellation eliminates the voltage offset due to RSW × Ibase. Finally, by properly choosing the gain "n" of the output amplifier, we can use process constraints (which could otherwise complicate the design) to our advantage.
使用T/H放大器技术对消隐电路，我们在主要进位转换期间在DAC输出端实现了非常小的毛刺（通常为10mV至20mV）。通过在RC反馈网络中实现零极点消除，消除了由于保持电容器引起的附加相移，并保持了输出放大器的稳定性。当采样开关断开时，仍通过电容器C1和C2采用负反馈。此外，基极电流消除消除了RSW×Ibase引起的电压偏移。最后，通过适当选择输出放大器的增益“n”，我们可以使用过程约束（否则可能使设计复杂化）以达到我们的优势。
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发表于 2023-2-16 12:54
